Current synthesis methodologies based on hardwaredescription languages focus mainly on two distinct levels: behavior and register-transfer levels. In many practical cases, however, the initial specification lies between a pure behavioral description and a completely structural one. This paper presents a method and algorithms for exploring the design space between the register-transfer and behav...

We present here a technique for allocation and binding for data path synthesis (DPS) using a Genetic Algorithm (GA) approach. This GA uses an unconventional crossover mechanism relying on a force directed data path binding completion algorithm. The data path is synthesized using some supplied design parameters. A bus-based interconnection scheme, use of multi-port memories, and provision for mu...

This paper proposes a novel genetic-based high-level synthesis methodology for ΣΔ modulators. This approach is based on simulation-based optimisation where optimal topology of the ΣΔ modulator is automated explored using a genetic algorithm(GA) under various design constraints, such as SNR(Signalto-Noise Ratio) and hardware complexity. The proposed synthesis technique has been implemented in Sy...

This paper presents the Flexible Architecture Representation , which is capable of representing complex hierarchical designs for synthesis as well as complex library components for hardware reuse. Contrary to previous representations used in high-level synthesis, the Flexible Architecture Representation supports multiple levels of controllers and thus enables a much larger degree of parallellis...

still not enough to satisfy all the LTCs and therefore serialized operations are folded if the total execution delay of the operations controlled by the places is smaller than the lower bound for the clock period. The only two places that can be folded together, given these criteria, are P 5 and P 6. Folding these two places decreases the length of all the LTCs and gives the control part in Fig...

This paper presents a new approach to hierarchical high-level synthesis with respect to internal register-transfer structures of complex components. Entire subdesigns can efficiently be used as complex components at a higher hierarchical level of the design. After synthesis, the calculated schedule of each subdesign is added to its register-transfer component model. This enables the sharing of ...

|In integer linear programming (ILP), formulating a \good" model is of crucial importance to solving that model [1]. In this paper, we begin with a mathematical analysis of the structure of the assignment, timing, and resource constraints in high-level synthesis, and then evaluate the structure of the scheduling polytope described by these constraints. We then show how the structure of the cons...

This extended abstract presents ThreadPoolComposer, a high-level synthesis-based development framework and metatoolchain that provides a uniform programming interface for FPGAs portable across multiple platforms.

In this paper, the problem of reducing switching activity in on-chip buses at the stage of high-level synthesis is considered, and a high-level low power bus binding based on dynamic bit reordering is proposed. Whereas conventional methods use a fixed bit ordering between variables within a bus, the proposed method switches a bit ordering dynamically to obtain a switching activity reduction. As...

This work presents the results obtained using a methodology that allows the hardware implementation and the rapid prototyping of communication protocols through Logic and High Level Synthesis. The implementation results of different description styles of protocols and a comparison among the protocol implementation using the High Level Synthesis technique with standard cells library and the impl...