A low voltage and power current differencing transconductance amplifier (CDTA) based on Floating gate MOSFET (FGMOS) Quasi-floating (QFGMOS) is presented. The use of QFGMOS eliminates confined in the floating gate, degraded gain-bandwidth product, silicon area etc. proposed circuits have been simulated using spice simulation software 180nm technology analog devices LtSpice XVII supply used for ...

We measured gate voltage-dependent Aharonov–Bohm oscillations in an InGaAs-based two-dimensional electron gas ring with a gate on top of one of the branches. After ensemble averaging, the h=e oscillation spectrum showed smooth oscillatory behavior as a function of the gate voltage. This could be a manifestation of the spin–orbit interaction induced interference. ? 2000 Elsevier Science B.V. All...

In the present paper we have done a comparative analysis of Dual Gate MOSFET having split gate architecture and conventional Dual Gate MOSFET architecture. Simulations have been performed using SILVACO-ATLAS tool, which shows significant improvement in characteristic of split gate architecture in comparison to the conventional structure. The split gate architecture consist two different materia...

This paper proposes a new short-circuit protection method for an IGBT. The proposed method is characterized by detecting not only gate charge but also gate voltage of the IGBT. This results in a shorter protection time, compared to the previous method that detects only the gate charge. A real-time monitoring system using an FPGA, A/D converters, and a D/A converter is used for the proposed prot...

This paper includes modeling and simulation of 180 MW units of pumped storage power plant with Variable speed machines. In this method, voltage source inverters are used instead of traditional cyclo-converters. This paper aims to control the voltage source inverters and maintain DC voltage at a constant value. AC/ DC/ AC converter is used in system configuration structure in order to control an...

A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si3N4 gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As the result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each...

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phaselocked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on Vctrl induced by the gate leakage current. The side effects induced ...

0026-2714/$ see front matter 2012 Elsevier Ltd. A http://dx.doi.org/10.1016/j.microrel.2012.06.022 ⇑ Corresponding author. Tel.: +82 2 2123 4619; fax E-mail address: [email protected] (I. Yun). In this paper, the characteristic degradations of multi-finger MOSFETs with different gate structures are experimentally investigated when the gate voltage stress is applied. Here, the degradations of th...

CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and ...