This work describes a framework for a GSN (Goal Seeking Neuron) Boolean neural network fast prototyping into a user-programmable gate array. This system provides a VHDL language description of the trained network, allowing the direct implementation of the circuit on an academic FPGA (Field-Programmable Gate Array). A GSN software tool was designed to train and simulate a user-defined network, w...

In this work, we demonstrate the use of a Field Programmable Gate Array (FPGA) as a physical platform for realizing chaotic delay differential equations (DDE). Moreover, using our platform, we also experimentally study the synchronization between two time delayed systems. We illustrate two different experimental approaches – one is hardware co-simulation (using a Digilent Atlys with a Xilinx Sp...

—After the appearance of Field Programmable Gate Array (FPGA), several systems have been built using FPGAs,thus called Reconfigurable System. The essence of Reconfigurable System is dynamically changing the circuit at runtime with the reconfigurable characteristic of Programmable Logic Devices to give the system advantages of both hardware and software. The thesis here starting from the basic t...

This paper presents a Xilinx Field Programmable Gate Array (FPGA) based speed control of AC Servomotor using sinusoidal PWM technique. Xilinx FPGA is a programmable logic device developed by Xilinx which is considered as an efficient hardware for rapid prototyping. It is used to generate 50 Hz sine wave, the triangular wave and the sinusoidal PWM signals. The sinusoidal pulse width controls the...

This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA’s SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The o...

Following the simple Programmable Logic Device (SPLD) and Field Programmable Gate Array (FPGA) generations a third generation of programmable logic technologies is now reaching the marketplace. These new architectures are driven by the move to system level integration and fast expanding markets such as networking and wireless communications which are not addressed adequately by mainstream FPGA'...

This paper reports on the implementation of an Artificial Neural Network (ANN) on an Atmel AT6005 Field Programmable Gate Array (FPGA). The work was carried out as an experiment in mapping a bit-level, logically intensive application onto the specific logic resources of a fine-grained FPGA. By exploiting the reconfiguration capabilities of the Atmel FPGA, individual layers of the network are ti...

Our paper presents the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) encoder and decoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. The solutions implemented on FPGA lead to a high calculation rate using parallelization. We implemented the BCH code in a 3s400FG456 FPGA. In this implementation we used 15 bit-size word code and the results show that the circuits w...

The asynchronous transfer mode (ATM) adaptation layer type 1 (AAL1) segmentation and reassembly (SAR) are designed and implemented by the field programmable gate array (FPGA). The SAR header is generated and processed in the FPGA and the SAR payload is stored in an external first-in–firstout (FIFO) device. A method to recover the source clock, called synchronous residual time stamp (SRTS), is i...

This paper examines the viability of using integrated programmable logic as a coprocessor to support a host CPU core. This adaptive coprocessor is compared to a VLIW machine in term of both die area occupied and performance. The parametric bounds necessary to justify the adoption of an FPGA-based coprocessor are established. An abstract Field Programmable Gate Array model is used to investigate...