Reliability is one of the fundamental considerations in the design of industrial control equipment. The microprocessor-based Hybrid Duplex fault-tolerant System (HDS) proposed in this paper has high reliability to meet this demand although its hardware structure is simple. The hardware configuration of HDS and the fault tolerance of this system are described. The switching control strategies in...

With our increasing dependency on computer-based systems, ensuring their dependability becomes one the most important concerns during system development. This is especially true for missionand safety-critical systems. Critical systems typically use fault tolerance mechanisms to mitigate run-time errors. However, fault tolerance modelling and, in particular, rigorous definitions of fault toleran...

This study is concerned with the performance modeling of a fault tolerant system consisting of operating units supported by a combination of warm and cold spares. The on-line as well as warm standby units are subject to failures and are send for the repair to a repair facility having single repairman which is prone to failure. If the failed unit is not detected, the system enters into an unsafe...

I make a rough estimate of the accuracy threshold for fault tolerant quantum computing with concatenated codes. First I consider only gate errors and use the depolarizing channel error model. I will follow P.Shor [1] for fault tolerant error correction (FTEC) and the fault tolerant implementation of elementary operations on states encoded by the 7-qubit code. A simple computer simulation sugges...

In a fault-tolerant parallel computer, a functional programming model can facilitate distributed checlq3ointing, error recovery, load balancing, and graceful degradation. Such a model has been implemented on the Draper Fault Tolerant Parallel Processor (FTPP). When used in conjunction with the FrPP's fault detection and masking capabilities, this implementation results in a graceful degradation...

The architecture of a fault-tolerant embedded computer system is presented. It employs multiple processors for high performance and dual-port memory units for interprocessor communication. The high performance embedded computer (HPEC) system consists of five processors that are partitioned into two sets namely the computing and IO partitions. The computing partition is concerned with computatio...

With our increasing dependency on computer-based systems, ensuring their dependability becomes one the most important concerns during system development. This is especially true for missionand safety-critical systems. Critical systems typically use fault tolerance mechanisms to mitigate runtime errors. However, fault tolerance modelling and, in particular, rigorous definitions of fault toleranc...

This paper presented a novel decentralized fault tolerant control strategy for the control of linear multivariable processes. The multiple model based fault tolerant method is used to improve system performance (under model uncertainty and slow variation) and implement active fault tolerant control. In the mean time, we extended the decentralized unconditional stable control to multiple model c...