Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components...

Parallel counters have been studied for several decades as a component in fast multipliers and multioperand adder circuits. Efficient design of these functional units can produce fast & efficient multipliers and signal processors. Proposed in this paper is a GF(2) generator polynomial expansion that can be used to specify parallel counters. The mathematical formalism provides a general way of d...

moving towards nanometer scales, quantum-dot cellular automata (qca) technology emerged as a novel solution, which can be a suitable replacement for complementary metal-oxide-semiconductor (cmos) technology. the 3-input majority function and inverter gate are fundamental gates in the qca technology, which all logical functions are produced based on them. like cmos technology, making the basic c...

Fast Fourier transform (FFT) coprocessor, having significant impact on the performance of communication systems, hasbeen a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recent...

Efficient modulo 2±1 adders are desirable for computer arithmetic units based on residue number systems (RNS) with the popular moduli set {2–1, 2, 2+1}. Regular n-bit ripple-carry adders or their fast equivalents are suitable for modulo 2 addition. But for the other two moduli a correcting increment/decrement step besides the primary n-bit addition is normally required. Several design efforts h...

In this paper, our main focus is to reduce computation delay proposed in previous FFA algorithm based FIR digital filter. Parallel FIR filter structure with fast finite-impulse response (FIR) along with symmetric coefficients reduces the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. . The proposed parallel FIR structures exploit the inherent nature of symme...

Quantum-dot cellular automata (QCA) is one of the best methods to implement digital circuits at nanoscale. It has excellent potential with high density, fast switching speed, and low energy consumption. Researchers have emphasized reducing number gates, delay, cell count in QCA technology. In addition, a ripple carry adder (RCA) circuit which each full adder's carry-out connection for next carr...

ABSTRACT: Several new generation wideband data communication systems nowadays, have adopted Orthogonal Frequency division Multiplexing technique. FFT/IFFT is one of the main kernel in the OFDM system, therefore, special attention needs to be given to optimize the FFT block. Hence, utilizing low power, area efficient as well as high speed multipliers and adders in Fast Fourier Transform will ens...