Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high frequency and RF circuits. This work presents for the first time, an s-parameter based analysis of the performance of RF circuits with various ESD protection designs. Additionally, a design methodology for distributed ESD protection using coplanar waveguides is developed to achieve a better im...

This paper presents a detailed investigation of the degradation of electrostatic discharge (ESD) strength with high gate bias for deep-submicron salicided ESD protection nMOS transistors, which has significant implications for protection designs where high gate coupling occurs under ESD stress. It has been shown that gate-bias-induced heating is the primary cause of early ESD failure and that t...

This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and Electro Static Discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5V/um Human Body Model (HBM) were demonstrated. Significant silicon area reduction was demonstrated in deep-sub micron...

To mitigate the radio-frequency (RF) performance degradation caused by electrostatic discharge (ESD) protection device, low capacitance (low-C) design on ESD protection device is a solution. With the smaller layout area and small parasitic capacitance under the same ESD robustness, silicon-controlled rectifier (SCR) device has been used as an effective on-chip ESD protection device in RF ICs. I...

In this paper, a circuit design method for electrostatic discharge (ESD) protection is presented. It considers the gate floating state for ESD protection and negatively gate biased for leakage suppression under normal operations. The circuit is achieved by adding a switch device and a negatively biased circuit at the gate of ESD protection devices. Robustness and leakage of ESD protection circu...

A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3....

Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parame...

BACKGROUND Development of longer term stroke rehabilitation services is limited by lack of evidence of effectiveness for specific interventions and service models. We describe the protocol for a multicentre randomised controlled trial which is evaluating an extended stroke rehabilitation service. The extended service commences when routine 'organised stroke care' (stroke unit and early supporte...

A V-band low-noise amplifier (LNA) with electrostatic discharge (ESD) protection using RF junction varactors is demonstrated in a 65-nm CMOS technology. The gate-source junction varactor is used to achieve a power-constrained simultaneous noise and input matching, and also as an auxiliary ESD protection for the NS and ND modes. The measured results shows an over 2.0-kV ESD protection in the PD ...

BACKGROUND For endoscopic resection of early GI neoplasia, endoscopic submucosal dissection (ESD) achieves higher rates of complete resection (R0) than endoscopic mucosal resection (EMR). However, ESD is technically more difficult and evidence from randomised trial is missing. OBJECTIVE We compared the efficacy and safety of ESD and EMR in patients with neoplastic Barrett's oesophagus (BO). ...