Since at the regime of nanometer, quantum confinement effects are observed and wave nature electrons is more dominant. Therefore, classical approach current formulation in mesoelectonics nanoelectronics results inaccuracy as it does not consider effect, which only applicable for bulk electronic device. For accurate modeling simulation nanoelectronics, device atomic-level mechanical models requi...

Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs different geometrical configurations NSFET. In this script, performance 3D GAA NSFET analyzed by varying device's width and thickness. Moreover, gate length scaled from 20 nm to 5 check device suitability continuous logic applicat...

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of proposed transistor. Different sensitivity AJ DG such as drain extension, length overlapping oxide thickn...

In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to gate length of 12 nm with Contact poly pitch (CPP) 48 is simulated. NS-TFET investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism P-I-N layout has been incorporated in the nanosheet devices...

GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted much attention owing to the low-cost and large area availability of Si substrate. In this paper, 90-nm-gate-length InAlN/GaN HEMT was fabricated device electrical properties were studied. The presents a low drain-induced barrier lowing (DIBL) 43 mV/V, parasitic source resistance (RS) 0.91 ??mm, peak intrinsic tra...

We investigate the performances of 18 nm gate length AlInN/GaN, InP/InGaAs heterostructure and a Silicon double gate MOSFET, using 2D Sentaurus TCAD simulation. The heterostructure device uses lattice-matched wideband Al0.83In0.17N /InP and narrowband GaN / In0.53Ga0.47As layers, along with high-k Al2O3 as the gate dielectric, while silicon based device uses SiO2 gate dielectric. The device has...

In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL). To assess the performance of the proposed structure, some device characteristics of the structure have been compared ...

The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. device also simulated using Silvaco simulator. Both and simulation results are compared found match closely. Quasi 3-D modeling approach adopted here determine surfa...

A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in form of a sheet. The mNS-FET has superior for stacked channels; consequently, it can significantly reduce short-channel effect (SCE); however, punch-through inevitably occurs bottom portion that is not surrounded by gates, resulting large leakage current. Moreove...

In this paper, the performance of GaAs and GaSb based sub-10 nm double-gate junctionless metal-oxide-semiconductor field-effect transistors (DG-JLMOSFETs) have been studied for high-performance switching applications. The quantum transmitting boundary method (QTBM) has considered electron transport, band structures are accounted sp3d5s* tight-binding modeling. channel thickness, t <sub xmlns:mm...