ABSTRACT The further improvement of nanoscale electron devices requires support by numerical simulations within the design process. After a briefly description of our 2D/3D-device simulator SIMBA, the results of the simulation of DG-MOSFETs are represented. Starting from a basic structure with a gate length of 30 nm, a calibration of model parameters was done based on measured values from liter...

The operation of 1–3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, large influence of substrate depletion underneath the buried oxide, absence of drain current transients, degradation in electron mobility are typical effects in these ultra-thin MO...

Turn-on efficiency is the main concern for silicon-controlled rectifier (SCR) devices used as on-chip electrostatic discharge (ESD) protection circuit, especially in deep sub-quarter-micron CMOS processes with much thinner gate oxide. A novel double-triggered technique is proposed to speed up the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the...

A silicon nanowire field effect transistor (FET) straddled by the double-gate was demonstrated for biosensor application. The separated double-gates, G1 (primary) and G2 (secondary), allow independent voltage control to modulate channel potential. Therefore, the detection sensitivity was enhanced by the use of G2. By applying weakly positive bias to G2, the sensing window was significantly broa...

An analytical compact model for the asymmetric lightly doped Double Gate (DG) MOSFET is presented. The model is developed using the Lambert Function and a 2-dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the net charge and channel current of the DGMOSFET are derived in section 2. Results for the channel potential and current are compared with 2-D numerical ...

A fine-grained reconfigurable architecture based on double gate technology is presented. The logic function operating on the first gate of a double gate (DG) transistor is reconfigured by altering the bias on its second gate. A compact reconfigurable cell is proposed that merges two stacked 3-state resonant tunneling devices and non-silicon transistors and “hides” the cost of reconfiguration by...