A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40 ) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fastlocking coarse acquisition is achieved in fo...

Since very short pulse waves are transmitted, UWB systems have excellent accuracy in terms of distance measurement. In order to measure the distance between the terminals, the transmitted pulses have to be synchronized by a delay-lock-loop (DLL) in the receiver. In this paper the performance of the DLL is evaluated. Its performance depends the timing jitter between the local clocks of the termi...

This paper presents a variable delay line DLL circuit implemented in a 0.8 m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The DLL circuit is capable of reducing clock skew from 1-3ns to below 500ps for clock frequencies from 50Mhz ...

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a firstorder DLL and an overdamped second-order DLL. The amount of jitter peaking is s...

The synchronization of the received pseudorandom (PRN) code and the local generated replica is fundamental to compute user position in Global Navigation Satellite System (GNSS) receivers. The more accurate correlation output and Delay Locked Loop (DLL) code tracking error are described in this paper from the hardware receiver point of view. Estimation is based on the number of samples per code ...

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-l...

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows ...

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect...

Propositional satisfiability (SAT) is a success story in Computer Science and Artificial Intelligence: SAT solvers are currently used to solve problems in many different application domains, including planning and formal verification. The main reason for this success is that modern SAT solvers can successfully deal with problems having millions of variables. All these solvers are based on the D...