Turing machine space complexity is related to circuit depth complexity. The relationship complements the known connection between Turing machine time and circuit size, thus enabling us to expose the related nature of some important open problems concerning Turing machine and circuit complexity. We are also able to show some connection between Turing machine complexity and arithmetic complexity.

In many applications of circuit design and synthesis, it is natural and in some instances essential to manipulate logic functions and model circuits using word-level representations and arithmetic operations in contrast to bit-level representations and logic operations. This paper reviews linear word-level structures and formulates their properties for combinational circuit modeling. The paper ...

This dissertation presents the results of my research in two areas: parallel algorithms/circuit complexity, and algorithmic motion planning. The chapters on circuit complexity examine the parallel complexity of several fundamental problems (such as integer division) in the model of small depth circuits. In the later chapters on motion planning, we turn to the computationally intensive problem o...

The boolean circuit complexity classes AC ⊆ AC[m] ⊆ TC ⊆ NC have been studied intensely. Other than NC, they are defined by constant-depth circuits of polynomial size and unbounded fan-in over some set of allowed gates. One reason for interest in these classes is that they contain the boundary marking the limits of current lower bound technology: such technology exists for AC and some of the cl...

The use of a rewrite-based theorem prover for verifying properties of arithmetic circuits is discussed. A prover such as Rewrite Rule Laboratory (RRL) can be used eeectively for establishing number-theoretic properties of adders, multipliers and dividers. Since veriication of adders and multipliers has been discussed elsewhere in earlier papers, the focus in this paper is on a divider circuit. ...

In ASIC design, arithmetic components are usually selected from tooland technology-dependent libraries providing very limited flexibility and choice of circuit structures. With the possibility of parameterized structural circuit descriptions at the gate-level in VHDL, versatile circuit generators can be implemented which are highly independent of tool platforms and design technologies. This ena...

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In this paper we associate to each multivariate polynomial f that is homogeneous relative to a subset of its variables a series of polynomial families Pλ(f) of m-tuples of homogeneous polynomials of equal degree such that the circuit size of any member in Pλ(f) is bounded from above by the circuit size of f . This provides a method for obtaining lower bounds for the circuit size of f by proving...