This paper presents an adaptive digital resolution improvement method for extrapolating and recursive analog-to-digital converters (ADCs). The presented adaptively enhanced ADC (AE-ADC) digitally estimates the digital equivalent of the input signal by utilizing an adaptive digital filter (ADF). The least mean squares (LMS) algorithm also determines the coefficients of the ADF block. In this sch...

We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processors. The converter quantizes and accumulates a binary weighted sequence of partial binary-binary matrix-vector products computed on the analog array, under presentation of bit-serial inputs in descending binary order. Th...

In this paper we describe an interline CCD imaging array which features high-speed, on-chip, parallel A/D conversion. In addition, we present test results from fabricated devices. The imaging chip was fabricated through MOSIS in a double-poly 2:0m CCD/CMOS technology on a chip with total area 2:25mm 2:22mm. The chip is composed of two components, namely, a 28 39 pixel, interline imaging array a...