A Delay-Locked-Loop with a quasi-linear modified differential delay element is presented. By employing body feed technique in the bias circuit of delay cell in the Multi-Controlled-Delay-Line, applicable range for the controlled signal has been widen to under-threshold voltages, also the nonlinearity of the conventional current starved delay element the has been suppress by bias circuit. Moreov...

This paper presents an ultra-wide-range all-digital delaylocked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor’s leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600 kHz to 1.2GHz in the ...

This paper proposes a self-aligned sub-harmonically injection locked phase loop (SILPLL) in 180-nm Semi Conductor Laboratory (SCL) CMOS technology. In this work, an aperture detector (APD) based delay (DLL) with windowing technique is proposed to dynamically align the timing of pulse rising edge voltage controlled oscillator. contrast classical SILPLL, work replaces commonly deployed tri-state ...

Delay locked loops are an attractive alternative to VCO based phase locked loops due to their simpler design and inherent stability [1]-[3]. The primary disadvantage of conventional DLLs is their limited phase range, which limits their application to mesochronous environments. This dual DLL architecture combines several techniques to achieve unlimited phase shift, low jitter and large operating...

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The utilizes three-tap feed-forward equalization (FFE) architecture. relative delays between the taps are selectable increments of 1/16th unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It also possible to control output amplitude source impedance for each tap programmable ar...

Delay-locked loops are an attractive alternative to VCO-based phase-locked loops due to their simpler design and inherent stability [1-3]. The primary disadvantage of conventional DLLs is limited phase range, that limits their application to mesochronous environments. This dual DLL architecture combines several techniques to achieve unlimited phase shift, low jitter and large operating range. T...

iii ACKNOWLEDGEMENTS I would like to express my sincere gratitude and appreciation to everyone who has helped to make this thesis possible. I would like to deliver my special thanks to my wife and my parents for their love, support, and patience. My deep appreciation also goes to Alfred Andrew for their time and valuable suggestions. Finally, I owe gratitude to all of my friends and colleagues ...

Abstract Multipath propagation is a major source of error in global navigation satellite systems (GNSSs), especially urban environments. This because conventional GNSS receivers can provide biased range estimates that lead to positioning errors. In this paper, an Extended Kalman Filter (EKF)-based solution relies on multi-correlator structure proposed replace the delay locked loop (DLL...

High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking a...