OBJECTIVE To compare helmet noninvasive ventilation (NIV), in terms of patient-ventilator interaction and performance, using 2 different circuits for connection: a double tube circuit (with one inspiratory and one expiratory line) and a standard circuit (a Y-piece connected only to one side of the helmet, closing the other side). METHODS A manikin, connected to a test lung set at 2 breathing ...

Rapid energy-delay exploration methodology based on circuit sizing as applied to clocked storage elements is presented. Circuit delay and energy are modeled using improved RC delay model of a transistor. The accuracy of the model is increased by using Logical Effort setup accounting for input signal slope and extraction of technology dependent parameters. The minimal energy-delay curve is gener...

This paper presents the development of delay pulse circuit with 1ns resolution for both driving ultrasonic array transducers and digital receive beamforming for ultrasonic phased array system. The circuit which can supply pulses with a 1ns time resolution employs the phase shifting with phase locked loop (PLL). In this way, 6 phase clocks with 1ns phase difference are generated, which are used ...

The maximum speed of synchronous circuits is generally constrained by the worst case propagation delay, which limits the system clock frequency. Various techniques exist to manage the circuit delay, trading off speed for other system resources. One such approach is to equalize the rise and fall delay times. The primary design parameter for equalizing these delay times is the ratio between the w...

Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gate-level circuits. In this paper , we study the complexity of two diierent minimum-delay gate resizing problems for combinational circuits composed of single-output gates. The rst problem is that of gate resizing for minimum circuit delay under the load-dependent delay model. The second problem...

A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In t...

The resistive-inductive-capacitive behavior of long interconnects which are driven by CMOS gates are presented in this paper. The analysis is based on the π-model of a RLC load and is developed for submicron devices. Accurate and analytical expressions for the output load voltage, the propagation delay and the short circuit power dissipation have been proposed after solving a system of differen...

As MOSFET sizes and wire widths become very small in recent years, in uence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC load. By representing the short-circuit curr...

We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay bu ers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays are not independent, a transistor sizing problem would require very complex non-linear optimization...

| We present formula of propagation delay for static CMOS logic gates considering short-circuit current and current owing through gate capacitance and using the n-th power law MOSFET model which considers velocity saturation e ects. The short circuit current is represented by a piece-wise linear function, which enables detailed analysis of the transient behavior of a CMOS inverter. We found tha...