This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions. key words: on-chip inter...

Der physikalische Entwurf digitaler Schaltungen auf der Basis logischer Grundzellen war lange Zeit „Stand der Technik“ und durch kommerzielle Entwurfswerkzeuge gut beherrscht. Mit der Verwendung von Deep-SubmicronTechnologien verlagern sich einerseits die wirksamen Signalverzögerungen von den Gattern zu den Verbindungsleitungen, andererseits ist die Optimierung der Verbindungsstrukturen in nich...

Chip cooling is an attractive option for leakage control and power as well as thermal management of high performance ICs. Subthreshold leakage being the main leakage contributor in nanoscale CMOS, it rapidly increases with scaling due to continuous reduction in the supply voltage and is highly temperature sensitive. The authors in this work investigate Si bulk nMOSFETs using both constant volta...

In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to c-ray irradiation is studied b...

The growing demand for high density VLSI circuits the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chip‟s total power consumption. Motivated by emerging battery-operated application on one hand and shrinking techn...

Present state-of-the-art CMOS technologies integrate MOS transistors with a minimum gate length of 0.18 Pm0.25 Pm and operate with a maximum power supply of 2.5 V. The thin gate oxide used in these technologies has a high tolerance to total dose effects. Therefore, circuits designed in these technologies using dedicated layout techniques (enclosed layout transistors and guard-rings) show a tota...

Estimation and Synthesis for Low Power, High Performance Integrated Circuits by Premal Buch Doctor of Philosophy in Engineering Electrical Engineering & Computer Sciences University of California, Berkeley Professor A. Richard Newton, Chair Power minimization is becoming very important for a number of reasons ranging from an increasing demand for portable computing to the problem of hot chips d...