This paper reports on the design and development of custom animation software to enhance comprehension and design of micro-processing systems. The purpose of the custom software is to be used as a tool for teaching second/third year undergraduate computer/electrical engineering students the basic concepts surrounding microinstruction based microprocessors and systems. The tool enhances comprehe...

In this invited talk, we characterize the approaches taken to form customized processors using combinations of programmable processors and Field Programmable Gate Arrays (FPGAs). We investigate these approaches by considering how and where customization takes place. We consider approaches to customize within a processors ISA, and external to the ISA. We also consider how processor customization...

This paper presents design of a custom architecture for Discrete Cosine Transform (DCT) using No-Instruction-Set Computer (NISC) design flow that is developed for fast processor customization. Using several software transformations and hardware customization, we achieved up to 10 times performance improvement, 2 times power reduction, 12.8 times energy reduction, and 3 times area reduction comp...

design space exploration, VLIW, systolic array, cache This paper addresses the problem of automated design of a computer system for an embedded application. The computer system to be designed consists of a VLIW processor and/or a customized systolic array, along with a cache subsystem comprising a data cache, instruction cache and second-level unified cache. Several algorithms for "walking" the...

This paper presents a non-intrusive framework for runtime verification of executable microcontroller code. A dedicated hardware unit is attached to a microcontroller, which executes the program under scrutiny, to track atomic propositions stated as assertions over program variables. The truth verdicts over the assertions are the inputs to a custom-designed μCPU unit that evaluates past-time LTL...

This paper presents an SIMD processor array dedicated to the implementation of neural networks. The heart of this machine is a systolic array of simple processing elements (PEs). A VLSI custom chip containing 2 2 PEs was built. The machine is designed to sustain suucient instruction and data ows to keep a utilization rate close to 100 %. Finally, this computer is intended to be inserted in a ne...

Media processing applications typically involve numerical blocks that exhibit regular floating-point computation patterns. For processors whose architecture supports only integer arithmetic, these patterns can be profitably turned into custom operators, coming in addition to the five basic ones (+, −, ×, / and √ ), but achieving better performance by treating more operations. This thesis addres...

This paper presents an SIMD processor array dedicated to the implementation of neural networks. The heart of this machine is a systolic array of simple processing elements (PEs). A VLSI custom chip containing 2 2 PEs was built. The machine is designed to sustain suucient instruction and data ows to keep a utilization rate close to 100 %. Finally, this computer is intended to be inserted in a ne...