This paper presents 10-bit, 1.5 MS/s, 2.5V, Low Power Pipeline analog to digital converter using capacitor coupling techniques. A capacitance coupling folded-cascade amplifier effectively saves the power consumption of gain stages of ADC in a 0.25 μm CMOS technology. The ADC also achieves Low power Consumption by the sharing an op-amp between two successive pipeline stage further reduction of p...

A proposed third-order noise-shaping accelerometer interface circuit enhances the signal-to-noise ratio, compared with previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled correlated double sampling integrator is proposed. This scheme functions even with large parasitic capacitances between the sensor and the interface circ...

This work proposes a 10b 170MS/s 0.18um CMOS pipeline ADC based on a double-channel op-amp sharing scheme to minimize power consumption. All the amplifiers of the ADC are continuously processing dual-channel signals regardless of clock phases. The measured differential and integral nonlinearities of the ADC are less than 0.31LSB and 0.72LSB. The prototype ADC with an active die area of 1.28mm s...

The transimpedance or current feedback operational amplifier (CFB op-amp) is reviewed and compared to a conventional voltage mode op-amp using an analysis emphasizing the basic feedback characteristics of the circuit. With this approach the paradox of the constant bandwidth obtained from CFB op-amps is explained. It is demonstrated in a simple manner that the constant gain-bandwidth product of ...

A proposed third order noise shaping accelerometer interface circuit enhances the SNR compared with the previ ously presented interface circuits The solution for the two chip implementation is described and a novel cross coupled CDS integrator is proposed This scheme functions even with the large parasitic capacitances between the sensor and the interface circuit The op amp noise is rst order s...

The presented work deals with analysis of non-ideal effect of pipelined analog-to-digital converter (ADC) such as random capacitor mismatch, comparator offset and finite op-amp gain. These factors arise during a conversion in the pipelined ADC when using CMOS technology and switched-capacitors (SC) technique. The pipelined ADC was simulated in MATLAB-Simulink simulation environment. Key-Words: ...

T h e technique of mirror biasing i s introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize i ts output voltage to bias variations. Various performance metrics like low frequency common mode and power supply rejection ratios, slew rate and the sensitivity of the systematic offset are substantially improved. The improved performance i s theoretically p...

A 1 V rail-to-rail constant-gm CMOS operational amplifier is proposed. This study shows that keeping the sum of currents in the complementary differential pairs constant rather than controlling the tail currents produces a constant-gm input stage operating in the weak inversion. The currents in the n-channel differential pair are regulated to keep the sum of currents in the complementary differ...

A current mode feedback operational amplifier designed using a complimentary MOS circuit technology has been discussed in this paper. A class AB amplifier has been used in the design and the design results in improvement of values of number of parameter when compared to the previously reported architecture. The circuit is designed using 0.35μm technology. Bandwidth of the presented architecture...

The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the given performance specifications while minimizing a cost function, such as a weighted sum of the active area and power dissipation. The approach is based on the observation that the first order behavior of a...