ADC-based CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sample the signal at 1× or 2× the baud rate. The 1× CDR aligns the sampling clock with the signal using a phase-tracking feedback loop [1-2], which requires a voltage-contr...

This article presents a data-startable baseband logic featuring gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up receivers (WuRxs). At each transition, the phase misalignment between coming from analog front-end (AFE) is cleared by GO-CDR circuit, thus allowing reception of long streams. Any free-running frequency mismatch GO bitrate does not limit number receivabl...

The paper describes a novel method for simple estimation of jitter contained in a received digital signal. The main objective of our research was to enable a noninvasive measurement of data link properties during a regular data transmission. To evaluate the signal quality we estimate amount of jitter contained in the received signal by utilizing internal signals of a data recovery circuit. The ...

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of bit width adjustment, 40:2 multiplexer, 2:1multiplexer, and current-mode logic driver with 3-tap feedforward equalizer. receiver has two-stage continuous-time linear equalizer, 2-tap half-rate fully adaptive decision-feedback phase interpolation-based digit...

Advent of multimedia applications, which require data links with ever-increasing capacity, is necessitating highspeed optical communication systems and driving research and development for high-speed ICs operating at 40 Gb/s. These optical fiber communication systems require high performance and low power chipsets, which incorporate useful service functions. Figure 1 illustrates a typical recei...

A blind-oversampling CDR tracks the high-frequency jitter of the input data stream, but is limited at low-frequencies by the size of its FIFO [1]. A phase-tracking CDR, on the other hand, tracks jitter at frequencies below f3dB of its loop filter, but performs poorly beyond this frequency [2]. In this paper, a semi-blind-oversampling technique is presented. The proposed technique produces a jit...

introduction:it is well-recognized that collimator-detector response (cdr) is the main image blurring factor in spect.  in this research, we compensated the images for cdr in molecular spect by using stir reconstruction framework. methods: to assess resolution recovery capability of the stir, a phantom containing five point sources along with a micro derenzo phantom were investigated. influence...

Clock buffers constitute a major source of power dissipation in VLSI circuits. In CMOS the load is primarily capacitive and hence an inductive shunt can reduce real power needs. This almost-adiabatic topology is referred to as a resonant buffer. Two resonant buffers can be actively controlled by additional variable capacitance, to deliver quadrature signals from a single incoming clock. The cos...