A generalized parameter-level statistical MOS model, called SMOS, capable of generating statistically significant model decks from intraand inter-die parameters statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo app...

To encourage continued investments in R&D to result in technological advancements in the field of microelectronics, protection of Intellectual Property Rights (IPR) embedded in the layout designs is a very important issue. In Thailand, protection is provided for the layout design of integrated circuits through the Protection of Layout-Designs of Integrated Circuits Act, B.E. 2543 (2000). The la...

The paper addresses some insights into the Euler path approach to find out the optimum gate ordering of CMOS logic gates. Minimization of circuit layout area is one of the fundamental considerations in circuit layout synthesis. Euler path approach suggests that finding a common Euler path in both the NMOS and PMOS minimizes the logic gate layout area. In this article, the minimization of layout...

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, whic...

In this paper a novel design of all-optical half-subtractor based on nonlinear directional coupler is proposed. By using four waveguides and appropriately adjusting the refractive indices and selecting the proper length of waveguides, halfsubtractor function can be obtained. The operation of this function is simulated by RSoft CAD-Layout (BeamPROP) simulator. The simulation results confirm the ...

When I started writing this article I thought a " cookbook " approach would be appropriate when describing the implementation of a good 12-bit layout. My assumption behind this type of approach was that a reference design could be provided, which would make the layout implementation easy. But I struggled with this topic long enough to find that this notion was fairly unrealistic. Because of the...

ion Levels 3 Behavior (Function) Structure (Netlist) Physical (Layout) Logic Circuit Processor System

Guillotine partitions play an important role in many research areas and application domains, e.g., computational geometry, computer graphics, integrated circuit layout, and solid modeling, to mention just a few. In this paper we present an exact summation formula for the number of structurally-different guillotine partitions in d dimensions by n hyperplanes, and then show that it is Θ (( 2d− 1 ...

Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching ...