The sustained growth in VLSI technology is fuelled by the continued shrinking of transistor to ever smaller dimension. The benefits of miniaturization are high packing densities, high circuit speed and low power dissipation. Binary multiplier is an electronic circuit used in digital electronics such as a computer to multiply two binary numbers, which is built using a binary adder. A fixed-width...

The sustained growth in VLSI technology is fuelled by the continued shrinking of transistor to ever smaller dimension. The benefits of miniaturization are high packing densities, high circuit speed and low power dissipation. Binary multiplier is an electronic circuit used in digital electronics such as a computer to multiply two binary numbers, which is built using a binary adder. A fixed-width...

We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carry-based adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4...

The most fundamental operation of any processor is the addition. For any circuit there are two important parameters that comes into count is high speed and low power consumption. Hence the speed of various modules should be maximized to dominate overall performance. Depending upon these parameters various adders can be invented like Carry Look Ahead Adder(CLA),Carry Skip Adder(CSA) and Ripple C...

A novel synchronous dual-bit adder design, realized using the elements of commercial standard cell libraries is presented in this article. The adder embeds two-bit carry look-ahead generator functionality and is realized using simple and compound gates of the standard cell library. The performance of the proposed dualbit adder design is evaluated and compared vis-à-vis the conventional full add...

This paper describes the work done towards design and implementation of multiplier modules using high speed architectures based on the concept of Vedic Mathematics. Unlike other Vedic multipliers where entire architecture is based on generating partial products in parallel and adding them, here the partial products for top level entity are adjusted using concatenation operation and are added us...

Reversible logic is playing a significant role in quantum computing as quantum operations are unitary in nature. Quantum computer performs computation at an atomic level; thereby doing high performance computations beyond the limits of the conventional computing systems. Reversible arithmetic units such as adders, subtractors, multipliers form the essential component of a quantum computing syst...

not repeated. This prevents attacks like a probable text attack. Second, we incorporate error-correcting codes and the result is that our scheme provides an error detection and correction capability. Storage requirements for public keys are about 3 x lo5 bits, if n is about 300 or 400 bits. In addition, under this scheme, the sender has a very light load, while the receiver bears a heavy comput...