The design and architecture of a reconngurable memory BIST unit is presented. The proposed memory BIST unit could accommodate changes in the test algorithm with no impact to the hardware. Diierent types of march test algorithms could be realized using the proposed memory BIST unit and the proposed architecture allows addition and elimination of the memory BIST components. Therefore memories wit...

When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the seria...

.............................................................................................................................. ii Acknowledgements ............................................................................................................ iii List of Figures .................................................................................................................... vi L...

In this paper, we present a BIST technique that measures the RMS value of a Gaussian distribution period jitter. In the proposed approach, the signal under test is delayed by two different delay values and the probabilities it leads the two delayed signals are measured. The RMS jitter can then be derived from the probabilities and the delay values. Behavior and circuit simulations are performed...

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes perform testing concurrently with the operation of the circuit. In this paper a novel input vector monitoring concurrent BIST scheme is presented that compares favorably to previously proposed schemes with respe...

The design and architecture of a memory test synthesis framework for automatic generation, insertion and veriication of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The exibility and eeciency of the framework are demonstrated by showing that memory BIST units with diierent architecture and characteristics could be...

1 This work was supported by DFG grant WU 245/1-3 Abstract Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The de...

In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power /energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.

The thesis consists of three sections, developing models of intuitionistic set theory in suitable categories. First, the categorical framework in which models are constructed is reviewed, and the theory of all such models, called Basic Intuitionistic Set Theory (BIST), is stated; second, we give a notion of an ideal over a category, with which one can build a model of BIST in which a given topo...