Indirect branch prediction is important to boost instruction-level parallelism in modern processors. Previous indirect branch predictions usually cannot achieve high performance for the ineffectiveness of correlated information. This paper proposes the Compilerassisted value correlation (CVC), a hardware/software cooperative indirect branch prediction scheme. The key is to identify effective va...

[4] Alphu urchitecture hundbook, Digital Equipment Corporation, Maynard, MA, 1992. [SI T.-Y. Yeh and Y.N. Patt, “Two-level adaptive training branch prediction,” Proc. 24th ACMIIEEE Int ’1 Symp. and Workshop on Microarchitecture, pp. 51-61, Nov. 1991. [6] T.-Y. Yeh and Y.N. Patt, “Altemative implementations of two-level adaptive branch prediction,” Proc. 19th Annual Int’l Symp. on Computer Archi...

Dynamic branch predictors are popular because they can deliver accurate branch prediction without changes to the instruction set architecture or pre-existing binaries. However, to achieve the desiredprediction accuracy, existing dynamic branch predictors require considerable amounts of hardware to minimize the integerence effects due to aliasing in the prediction tables. We propose a new dynami...

Conditional branches limit the speed of modern microprocessors. Researchers need tools to examine program branch behavior. HALT, the Harvard Atom-Like Tool, allows SUIF users to instrument conditional branch instructions in their programs. Instrumentation code enables research into the branch problem: how programs use conditional branches and how they can be handled efficiently during program e...

Predictors are inevitable components in the state-of-theart microprocessors and branch predictors are actively discussed from many aspects. Performance of a branch predictor largely depends on the dynamic behavior of the executing program, however, we have no effective metrics to represent the nature of program behavior quantitatively. In this paper, we introduce an information entropy idea to ...

A CMOS eight-transistor (8T) memory cell is used for a complete proposed SRAM design. The proposed output buffer, eliminating the use of sense amplifier with all its synchronization schemes, exploits a cost-effective of overhead circuitry, and more important reduces the power consumption by a rate of 43% in comparing to 6T SRAM. Furthermore, the cell contributes a silicon area of 30% larger tha...

Without special handling branch instructions would disrupt the smooth flow of instructions into the microprocessor pipeline. To eliminate this disruption, many modern systems attempt to predict the outcome of branch instructions, and use this prediction to fetch, decode and even evaluate future instructions. Recently, researchers have realized that the task of branch prediction for processor op...

Two-level predictors deliver highly accurate conditional branch prediction, indirect branch target prediction and value prediction. Accurate prediction enables speculative execution of instructions, a technique that increases instruction level parallelism. Unfortunately, the accuracy of a two-level predictor is limited by the cost of the predictor table that stores associations between history ...

Branch prediction is a key mechanism used to achieve high performance on multiple issue, deeply pipelined processors. By predicting the branch outcome at the instruction fetch stage of the pipeline, superscalar processors are better able to exploit Instruction Level Parallelism (ILP) by providing a larger window of instructions. However, when a branch is mispredicted, instructions from the misp...

Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors. Though many dynamic branch predictors have been proposed to obtain high prediction accuracy, they cannot perform as expected under context switches. It is observed that context switches, even at fairly large intervals, can seriously degrade the performance of dynamic branch predictors. In...