In digital signal processors multipliers play a major role because, high multiplication process is carried out in hardware part in digital circuits. Array multiplier also requires less space for implementation in ICs and is an efficient way of multiplication in digital integrated circuits [3-4]. In this paper we have designed and analysed a four bit array multiplier using 45nm CMOS process. Arr...

The multiplier is the building block required in the adaptive equalizer that is most costly in terms of both speed and power. Since the power consumed by a CMOS digital circuit is CV 2 f, reducing the power supply and employing one or a combination of parallelism and pipelining can result in a significant power savings [4]. Applications using a power supply of 3.3 V are becoming widespread in o...

In computer science and digital electronics, a bit matrix multiplier (BMM) is mathematical operation that used to quickly multiply binary matrices. BMM basic component of many algorithms utilized in fields including machine learning, image processing, cryptography. creates new represents the product two input matrices by performing logical AND XOR operations on each element’s value. crucial met...

The two-bit multiplier is a simple electronic circuit, small enough to be evolvable, and practically useful for the implementation of many digital systems. In this paper, we study the structure of the two-bit multiplier fitness landscapes generated by circuit evolution on an idealised model of a field-programmable gate array. The two-bit multiplier landscapes are challenging. The difficulty in ...

In this paper, we present flexible multi-precision multiplier that combined variable precision, parallel processing (PP), razor based dynamic voltage scaling (DVS), and dedicated MP operand scheduling to provide optimum performance for variety of operating conditions. All of the building blocks of proposed flexible multiplier can either work as independent small precision multiplier or parallel...

This paper proposes a novel and area efficient bit serial multiplier architecture in which both the multiplier and multiplicand are processed in real time. The major advantage of proposed multiplier is the bit serial data which results in reduced area and simple circuitry, the use of compressor enables us to get bit serial out put every clock cycle. The proposed architecture is best suited for ...

The multiplication operation is present in many parts of a digital system or digital computer, most notably in signal processing, graphics and scientific computation. With advances in technology, various techniques have been proposed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI imp...

This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the IEEE standard 754 for floating point multiplication, and tested for functionality in Verilog. The design, which was done in dual-rail domino, was simulated ...

We present a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512 128 vector-matrix multiplier on a single 3 mm 3 mm chip fabricate...

In this paper, we present a low complexity bit-parallel Montgomery multiplier for GF(2m) generated with a special class of irreducible pentanomials xm + xm−1 + xk + x + 1. Based on a combination of generalized polynomial basis (GPB) squarer and a newly proposed square-based divide and conquer approach, we can partition field multiplications into a composition of sub-polynomial multiplications a...