Difference between speed of processor and memory is increasing with advent of every new technology. Chip Multi Processors (CMP) have further increased the load on the memory hierarchy. So it has become important to manage on-chip memory judiciously to reduce average memory access time. The previous research has shown that it is better to have a shared cache at the last level of on-chip memory h...

Set associative caches have fixed ways. Entire cache is enabled during cache operation. This paper proposes cache architecture mapping cache line to fixed cache way of mapped set. The address is mapped to set as in conventional set associative cache. The tag value of the mapped line is divided into blocks of size of number of cache ways. The average of maximum and minimum frequency of this divi...

Client-side caching is an effective technique to hide network latency and improve I/O performance in network-based file systems. Current methods mainly adopt block-indexed caching structures, which suffer cache inefficiency problems in high concurrency environment. In this paper, we present a hybrid client-side caching scheme (HCCache) to avoid performance degradation caused by the block interl...

Wireless network applications, such as, searching, routing, self stabilization and query processing can be modeled as random walks on graphs. Stateless Opportunistic routing technique is a robust distributed routing technique based on random walk approach , where nodes transfer the packets to one of their direct neighbors uniformly, until the packets reach their destinations. Simplicity in exec...

Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. This paper proposes exclusive cache model that reduces the energy consumption over the tag cache model. The proposed model assumes two level exclusive cache with tag cache in level one. The tag cache consists of tag information of all cache levels. It is stored in cache in level one. An address is ...

The central data structures for many applications in scientific computing are large multidimensional arrays. These arrays dominate memory accesses and are often accessed with strides that vary across orthogonal dimensions posing a central and critical challenge to develop effective caching strategies. We propose a novel technique to optimize cache placement for multidimensional arrays with the ...

In the memory system of multivector processors, the interferences between concurrent vector streams cause the loss of cycles that makes the effective throughput be lower than the required throughput. Then, the work of the functional units is delayed. Using the classical order to access the vector stream elements, the vector stream references the memory modules using a temporal distribution that...

The performance of a vector processor accessing vectors is strongly dependent on the conflicts produced in the memory subsystem. These conflicts delay the job of the functional units. Conflicts named linked conflict and complex conflicts interfere the steady-state performance in complex memory systems (CRAY X-MP).This paper proposes a method to access vector streams that reduces the average mem...

In this paper, we demonstrate the effectiveness of application directed explicit cache management. We define the generalized split temporal/spatial cache architecture as an abstraction of several advanced cache architectures. We analyze individual problems, identify the inefficiencies in the memory hierarchy and develop explicit cache management algorithms. In our algorithms, the application so...