Signature analysis is an important compact method in digital testing. Applying this method, a test response sequence of a device under test is compressed by a linear feedback shift register (LFSR, for short). Masking occurs if a faulty device yields the same signature as the corresponding good device. Due to the linearity of any LFSR, this happens if and only if the 'error sequence' which is ob...

Testing of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the unprecedented levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power dissipation and test application time within acceptable limits. This dissertation proposes techniques to ...

Aim of this study is to focus on reducing test pattern with effective Linear Feedback Shift Register (LFSR) reseeding. Test data volume of modern devices for testing increases rapidly corresponding to the size and complexity of the Systems-on-Chip (SoC). LFSR is a good pseudorandom pattern generator, which generates all possible test vectors with the help of the tap sequence. It can achieve hig...

In this paper we extend the conditional correlation attack ([LCPP96]) against the nonlinear filter generator (NLFG) by introducing new conditions and generalisations and present two known-plaintext attacks, called hybrid correlation attack and concentration attack. The NLFG is a well known LFSR-based keystream generator which could be used as a basic building block in a synchronous stream ciphe...

Feedback with Carry Shift Registers (FCSRs) are a promising alternative to Linear Feedback Shift Registers (LFSRs) for the design of stream ciphers. The main difference between these two automata lies in the computation of the feedback. While LFSRs use simple bitwise addition, FCSRs use addition with carries. Hence, the transition function of an FCSR is non-linear, more precisely quadratic. Sin...

SSC2 is a stream cipher that operates by XORing the output of two \half-ciphers". The rst half-cipher is constructed from a linear feedback shift register (LFSR) with a non-linear lter. The second half-cipher is constructed from a lagged Fibonacci generator (LFG) and a multiplexor that chooses values from the Fibonacci register. The second half-cipher has a small cycle length 2. By XORing the k...

A new fault coverage test pattern generator using a linear feedback shift register (LFSR) called FC-LFSR can perform fault analysis and reduce the power of a circuit during test by generating three intermediate patterns between the random patterns by reducing the hardware utilization. The goal of having intermediate patterns is to reduce the transitional activities of Primary Inputs (PI) which ...

We introduce a new kind of word-oriented linear feedback shift register called σ−LFSR which is constructed with the instructions of the modern processor and have fast software implementation. We offer an algorithm to search for good primitive σ−LFSR. In particular, we give two examples HHZ-1 and HHZ-2 and compare their efficiency and security with those of the LFSRs appearing in stream ciphers ...

We describe a solution for physically obfuscating the representation of a cipher, to augment chips resistance against physical threats, by combining ideas from masking techniques and Physical Obfuscated Keys (POKs). With embedded chips – like RFID tags – as main motivation, we apply this strategy to the representation of a Linear Feedback Shift Register (LFSR). The application of this technique...

of BDDbased 32-bit CRC encoder and decoder using LFSR methodology, with low power and less area. Generally 32-bit CRC is used in Ethernet frame for fault recognition at the transmitted data. The functional required for LFSR implementation is shift registers, flip flop which works for high frequency and yields less delay and consumes less power, the TSPC flip flop which is suitable for high spee...