The current state of the art in integrated circuit design is based on the use of special hardware design languages such as VHDL. In the context of the development of an intelligent, knowledge-based debugging aid for VHDL programs, we are dealing with analysis and diagnosis of a subset of VHDL (which is similar to conventional concurrent programming languages). We present an adaptation of conven...

Described are VHDL related methods and experiences from the RASSP programs model year effort. The "Virtual Prototype” development methodology is presented highlighting specific VHDL model views and their interact ions with sof tware design. Performance and Instruction Set Archi tec ture model ing areas o f the methodology are elaborated drawing from the experiences of the Demonstration team. Fi...

In the high-level synthesis domain, the integration of user defined RT components in the algorithmic specification plays an important role. The implementation of VHDL models emulating specific functional and timing behavior at the algorithmic level is expensive and time-consuming. Moreover, particular functional and timing behavior can only be implemented at the RT level, e.g. interrupt handlin...

Testability analysis of VHDL sequential models is the main topic of this paper. We investigate the possibility to obtain information about the testability of a sequential VHDL description before its actual synthesis. The analysis is based on an implicit fault model that injects faults into a BDD based description extracted from the VHDL representation. Such an injection is related to the origin...

We describe the application of model-based diagnosis to the debugging of VHDL programs. In our previous work in VHDL-based software diagnosis, we have relied upon a very abstract representation to make it possible to diagnose fullsized applications (up to 1MLOC) at the cost of reduced discrimination between diagnoses. This paper describes a more detailed representation for VHDL programs that ex...

The paper describes a VHDL based hierarchical test generator for digital systems. A VHDL subset to be used as an input of the test generation system is defined. The VHDL description will be transformed into a set of decision diagrams, which is used as a diagnostic model of a system under test. Functional test generation as well as hierarchical test synthesis are supported by the model. Experime...

encountered in ASIC (applicationspecific integrated circuit) developments originate from unclear or incorrectly implemented specifications. To allow independent evaluation of a device’s functionality, the European Space Agency (ESA) normally requests a VHDL model before a company starts the detailed design. This allows ESA or another company to verify the functionality. (For more about ESA and ...