Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin...

FPGA systems can have a wide variety of applications within electrical engineering, product development, and prototyping. Their flexibility, low cost, and high performance has made it burst into the market with results that exceeded many expectations. National Instruments offers several software and hardware that integrate FPGA systems in their design and implementation. In this thesis work, a ...

This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in onchip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 3011s. Inactive memor...

This paper gives a brief introduction to the application-dependent FPGA testing. In comparison with the conventional application-independent FPGA testing whose objective is to test the resources of a FPGA chip as exhaustively as possible, application-dependent FPGA testing is only performed on the resources used by a specific application implemented on the FPGA. The multi-configuration strategy...

We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized ...

There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection sch...

Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We pres...