The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in progr...

We present a substantially improved version of our popular UDP/IP core for simple and fast PC ↔ FPGA communication over Gigabit Ethernet. We provide a novel feature to automatically configure (previously hard-coded) internal settings on the FPGA. Thereby, we substantially reduce the installation overhead when a FPGA shall communicate with several different PCs. The UDP/IP core is designed to oc...

In this paper, I present FPGA implementation of a digital down converter (DDC) and digital up converter (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the circuits are verified on the...

The concept of Image Processing is totally related to real time work, which is done by FPGA. Mathematical morphology is a well known image and signal processing technique. However, most morphological tools such MATLAB are not suited for strong real-time constraints. Application of FPGA Coprocessors as a means of delivering hardware IP to software and system engineers is presented. The hardware ...

This paper presents an area-efficient FPGA architecture for handshake-component-based design. The handshake-component-based design is suitable for largescale, complex asynchronous circuit because of its understandability. However, conventional FPGA architecture for handshake-component-based design is not area-efficient because of its complex logic blocks. This paper proposes an area-efficient F...

Design practices have an enormous impact on an FPGA design’s timing performance, logic utilization, and system reliability. Good design practices also aid in successful design migration between FPGA and ASIC implementations for both prototyping and production. Poor design practices can lead to low performance, high logic or resource utilization, and unstable or unreliable designs associated wit...