In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be challenge to design high performance low-power systems. Therefore, designers are trying reduce dissipation these systems by using optimization techniques. Different mathematical operations can found the archit...

Directly or indirectly adders are the basic elements in almost all digital circuits, three operand building blocks LCG (Linear congruential generator) based pseudo-random bit generators. Elementary fast, area and power efficient for small sizes. Carry save adder computes addition O(n) time complexity, due to its ripple carry stage. Parallel prefix such as Han-Carlson compute O(log(n)) complexit...

Conclusions Very large scale integrated (VLSI) circuits used in the space & nuclear industry are continuously subjected to ion radiation. As the limits of VLSI technology are pushed towards sub-micron levels in order to achieve higher levels of integration, devices become more vulnerable to radiation induced errors. These radiation induced errors can lead to system failure, particularly if they...

Demand for High Speed & Low Power Architecture for Image/Video Compression Algorithms are increasing with scaling in VLSI Technology many Architectures in the Discrete Wavelet Transform (DWT) System have been proposed. This Paper surveys the different designed DWT’s using Systolic Array Architectures and the Architectures are classified based on the application whether it is 1-D, 2-D or 3-D. Th...

The Finite Impulse Response (FIR) filters are widely used in many Digital Signal Processing (DSP) applications. For these applications, the low power, less area, high speed and low complexity FIR filter architectures are required. The researchers have proposed many FIR filters to meet the above design specifications. This paper is focused on the some efficient reconfigurable FIR filter architec...

∗ This work was supported in part by Nokia Corporation, Texas Instruments, Inc., the Texas Advanced Technology Program under grant 1997-003604-044, and by NSF under grants NCR-9506681 and ANI-9979465. Abstract Next-generation computing systems will be highly integrated using wireless networking. The Rice Everywhere NEtwork (RENÉ) project is exploring the integration of WCDMA cellular systems, h...

This paper presents several techniques for the VLSI implementation of the MAP algorithm. In general, knowledge about the implementation of the Viterbi algorithm can be applied to the MAP algorithm. Bounds are derived for the dynamic range of the state metrics which enable the designer to optimize the word length. The computational kernel of the algorithm is the Add-MAX* operation, which is the ...

The Benes network consists of back-to-back butterflies. There exist a number of topological representations that are used to describe butterfly like architectures. We identify a new topological representation of Benes network. The significance of this representation is demonstrated by solving two problems, one related to VLSI layout and the other related to robotics. An important VLSI layout ne...

Very large scale integration (VLSI) design methodology and implementation complexities of high-speed, low-power soft-input soft-output (SISO) a posteriori probability (APP) decoders are considered. These decoders are used in iterative algorithms based on turbo codes and related concatenated codes and have shown significant advantage in error correction capability compared to conventional maximu...