This paper illustrates the simulation of Vedic multiplier in 2D DCT. The input data is first divided into NxN blocks, each block s of 8x8 size and 2-D DCT is applied on each of these 8x8 block and 2-D DCT is applied to reconstruct the image. The proposed 2-D DCT design uses Urdhva Tiryagbhyam a Vedic multiplication sutra and the Simulations with MATLAB prove that the proposed design is compared...

This paper is devoted for designing high speed arithmetic logic unit. All of us know that ALU is a module which can perform arithmetic and logic operations. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the op...

A maximum of 110 elements exist within the Vedic Periodic Table of Elements, in contrast to the Periodic Table of Elements of western science. This paper describes the difference between the two tables and iterates the prediction by K.C. Sharma of the 110 th Element, X110, which is referred to in the Rig Veda, the oldest book known to humanity. Then, this paper provides the Combinatorial Vedic ...

The Papyrus of Ani illustrates the sub – atomic processes between the Thaamic Substratum of Dark Matter and its transformation into visible, stable 8 x 8 Satvic matter and dynamic 9 x 9 Rajic matter. Traditional interpretations explain the papyrus in reverse, from top to bottom, from left to right. In fact, the process begins with the Opening of the Mouth, the Weighing of the Osirian soul, and ...

In this paper, we describe adiabatic Vedic multiplier using efficient charge recovery logic (ECRL) and energy efficient adiabatic logic (EEAL). In today’s world low power hindrance have become a major important factor in modern VLSI design. Because of the increasingly draconian demands for battery space and weight in portable multimedia devices, energy productive and high yielding circuits are ...

In digital signal processing convolution is a fundamental computation that is ubiquitous in many application areas. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) methods are employed. In this paper, block convolution process is proposed using a multiplier architecture based on vertical and crosswise algorithm of Ancient Indian Vedic Mat...

In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per The proposed architecture, for two 8-bit numbers; th...

In this paper VHDL implementation of complex number multiplier using ancient Vedic mathematics and conventional modified Booth algorithm is presented and compared. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplicatio...

This paper proposes the hardware implementation of RSA encryption/decryption algorithm using the algorithms of Ancient Indian Vedic Mathematics that have been modified to improve performance. The recently proposed hierarchical overlay multiplier architecture is used in the RSA circuitry for multiplication operation. The most significant aspect of the paper is the development of a division archi...

A unique and increasingly pervasive feature within the tourism landscapes in post-modern world is special interests of tourists death anything associated with death. It often believed that those who indulge disaster site tours could potentially awaken their spiritual journey. The visitor immersions, spaces death, events have taken place or are re-created, triggers social conscience, some shared...