Progress in semiconductor process technology has made SO1 transistors ons of the most promising candidates for high pertormance and low power designs. With smaller diffusion capacitances, SO1 transistors switch significantly faster than their traditional hulk MOS counterparts and consume less power per switching. However, design and simulation of SO1 MOS circuits is more challenging due to more...

In this paper a method for choosing appropriate transistor topology for use with transistor sizing is presented. In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing in order to guarantee synchronously arriving signal slopes at the input of logic gates. Since the delay of a logic gate depends directly on transistor sizes, the variation of channel-...

In this paper, a new method of transistor chaining for 1-D automatic leaf cell synthesis is presented. The method allows synthesis of cells suitable for row-based layouts with no restrictions imposed on network topologies/transistor sizes. The novelty of the solution arises from transistor chaining with integrated dynamic transistor folding. We provide the theoretical analysis of transistor fol...

Development of all-magnetic transistor with favorable properties is an important step towards a new paradigm of all-magnetic computation. Recently, we showed such possibility in a Magnetic Vortex Transistor (MVT). Here, we demonstrate enhanced amplification in MVT achieved by introducing geometrical asymmetry in a three vortex sequence. The resulting asymmetry in core to core distance in the th...

Graphene, after its first production in 2004 have received lots of attentions from researchers because of its unique properties. High mobility, high sensitivity, high selectivity and high surface area make graphene excellent choice for bio application. One of promising graphene base device that has amazingly high sensitivity is graphene field-effect transistor (GFET). This review selectively su...

A complete procedure for the design of W-band low noise amplifier in MMIC technology is presented. The design is based on a simultaneously power and noise matched technique. For implementing the method, scalable bilateral transistor model parameters should be first extracted. The model is also used for transmission line utilized in the amplifier circuit. In the presented method, input/output ma...

The switching thresholds of magnetophoretic transistors for sorting cells in microfluidic environments are characterized. The transistor operating conditions require short 20-30 mA pulses of electrical current. By demonstrating both attractive and repulsive transistor modes, a single transistor architecture is used to implement the full write cycle for importing and exporting single cells in sp...

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline sil...

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene...