Field-programmable gate arrays (FPGAs) are often utilized in space avionics. To protect the FPGA logic against the ionizing radiation effects in space, redundancy in form of concurrent error detection can be used. In this work, we present a comparative study of a parity-based error detection with software-based retry, and a triple modular redundancy technique on a known flash-based FPGA archite...

Today’s designs have grown in size and complexity by orders of magnitude in comparison to common designs of only a few years ago. FPGAs have also grown in size and density, with 100k-gate FPGAs now available. Because of this growth in FPGA density, designs that previously required an ASIC implementation may now be targeted to an FPGA. However, schematic based design is no longer the ideal metho...

An Integration Circuit is an extremely complex task. It is continually stress the fact that the field is inherently multidisciplinary in nature. By keeping Very large scale integration as a reference we consider the field programmable gate array (FPGA) technology has become an advanced target for the implementation of real time algorithms suited to video image processing applications. The uniqu...

In the next few years, logic capacities for fieldprogrammable gate arrays are expected to exceed one million gates per device. While this expansion of FPGA device resources offers the promise of exceptional finegrained performance for developing technologies such as ASIC prototyping and FPGA computing, supporting computer-aided design tools have yet to be developed to target these devices rapid...

FPGA-based acceleration of molecular dynamics simulations (MD) has been the subject of several recent studies. The short-range force computation, which dominates the execution time, is the primary focus. Here we combine: a high level of FPGA-specific design including cell lists, systematically determined interpolation and precision, handling of exclusion, and support for MD simulations of up to...

This paper describes the implementation of a real-time video algorithm on a context-switched FPGA. The FPGA is based on the Xilinx XC4OOOE FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware. The algorithm makes use of special features of this architecture to achieve high utilization of the silicon at ...

This paper describes the framework of internal hardware templates. These reusable templates can be instantiated, inside the FPGA, to the required precision. Thus, the resource utilization of the target RCMs can be improved. Moreover, the configuration time can be eliminated after the first use of the template. The detail design is presented.