In this paper, we show that spatial joins are very suitable to be processed on a parallel hardware platform. The parallel system is equipped with a so-called shared virtual memory which is wellsuited for the design and implementation of parallel spatial join algorithms. We start with an algorithm that consists of three phases: task creation, task assignment and parallel task execution. In order...

In this Chapter, we have characterized the bus traffic generated by the SPECweb96 benchmark in a four-processor SMP system with NT/4 operating system. We observe that the benchmark is very network intensive, in terms of computation and bandwidth consumption. The study shows that the transactions across the four processors are well balanced and do not have any long-range dependencies. There is a...

Data variety, as one of the three Vs of the Big Data, is man-ifested by a growing number of complex data types such asdocuments, sequences, trees, graphs and high dimensionalvectors. To perform similarity search on these data, exist-ing works mainly choose to create customized indexes fordifferent data types. Due to the diversity of customized in-dexes, it is hard to dev...

In this paper we describe graph-based parallel algorithms for entity resolution that improve over the map-reduce approach. We compare two approaches to parallelize a Locality Sensitive Hashing (LSH) accelerated, Iterative Match-Merge (IMM) entity resolution technique: BCP, where records hashed together are compared at a single node/reducer, vs an alternative mechanism (RCP) where comparison loa...

A finite-difference Micromagnetic simulation code in MATLAB is presented with Graphics Processing Unit (GPU) acceleration. The high performance of Graphics Processing Unit (GPU) is demonstrated compared to a typical Central Processing Unit (CPU) based code. The speed-up of GPU to CPU is shown to be greater than 30 for problems with larger sizes on a mid-end GPU in single precision. The code is ...

Hypothesis Modern scalar processors inefficiently use fetch bandwidth when executing vectorizable code. By augmenting a general-purpose processor with a Stream Vector Processing Unit (SVPU), we can use the fetch bandwidth much more efficiently and achieve speed-ups in performance on vectorizable code. We also believe that by using a hierarchy of register files, this architecture will use memory...