DESIGN OF SECOND-ORDER SIGMA-DELTA MODULATOR USING CMOS TECHNOLOGY

A new design approach of a digital delta-sigma modulator with small output fluctuation is proposed. The digital delta-sigma modulators are used in the digital-analog converters, the fractional-N phase lock loop, etc. and its output fluctuation is one of the important performances although a higher order modulator often produces large fluctuations. In this work, the noise shaping filter of the m...

approved: Gabor C. Temes This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC c...

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of L th-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no ov...

Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. This type of modulator requires high-resolution test stimulus, which is difficult to generate. This paper proposes a novel and robust technique to determine the performance of the modulator by characterizing its key parameters using a pseudo-random pattern sequence. This technique is suitable for BIST appl...

In this paper, a novel class of Sigma-Delta modulators is presented. The usual scalar 1-bit quantizer in a Sigma-Delta modulator is replaced by a 1-bit vector quantizer with a Ndimensional input statevector from the linear feed-back fdter. Generally, the vector quantizer changes the nonlinear dynamics of the modulator, and a proper choice of vector quantizer can improve both system stabilitg an...

This paper describes an analog-to-digital converter which combines multiple delta–sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta–sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta–sigma modulators in parallel with no ove...

In this chapter we present an unified approach for study the stability and validation of potential limit cycles of one bit high order Sigma-Delta modulators. The approach is general because it uses the general form of a Sigma-Delta modulator. It is based on a parallel decomposition of the modulator and a direct nonlinear systems analysis. In this representation, the general N-th order modulator...

A major drawback of delta-sigma modulation is the high oversampling ratios required, especially for single-bit quantization. Accordingly, much of the research in the area has focused on lowering the sampling rate through various parallelization approaches. However, this research has been overwhelmingly concentrated on continuous and discrete-time analog modulator implementations for A/D convert...

The DC content in single-bit domain is both undesirable and hard to remove. In this paper we propose a single-bit multiplierless DC-blocker structure. The input is assumed to be sigma-delta modulated bitstream. This DC-blocker is designed using a delta modulator topology with a sigma-delta modulator (SDM) embedded in its feedback path. Its performance is investigated in terms of the overall sig...