In this paper we introduce an offline digital calibration technique that allows the feed-forward residue compensation (FRC) architecture to provide a 70-Msps 15-bit converter with a final spurious-free dynamic range (SFDR) of over 100dB. We develop analytical expressions for the maximum accuracy that can result from this architecture. Simulations of the overall architecture including device mis...

about the device design and fabrication process can be found in [1,2,7]. Abstract: The first demonstration of both analog and digital wavelength conversion using an InP monolithicallyintegrated widely-tunable wavelength converter is reported. The SFDR was measured to be better than 82.7 dB-Hz and a BER of better than 10 at 2.5Gbps over a wide wavelength range (50nm input, 22nm output) with a po...

A 12-b 20-MS/s pipelined ADC is calibrated using an algorithmic ADC, which is itself calibrated. With background calibration, the peak SNDR and SFDR of the pipeline are 70.8 dB and 93.3 dB, respectively. The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm in 0.35 m CMOS.

This paper presents an efficient technique to extremely increase the performance of Pedersen’s digital chirp generator concerning the level of the Spurious-Free Dynamic Range (SFDR) and size of the memory. The proposed digital chirp generator uses the piecewise parabolic interpolation to decrease the memory size and system complexity while maintaining excellent spectral performance in compariso...

this paper presents a modified 32-bit rom-based direct digital frequency synthesizer (ddfs). maximum output frequency of the ddfs is limited by the structure of the accumulator used in the ddfs architecture. the hierarchical pipeline accumulator (hpa) presented in this paper has less propagation delay time rather than the conventional structures. therefore, it results in both higher maximum ope...

The paper studies a unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3-dimensional (3D) layout, to improve its spurious-free dynamic range (SFDR) communication applications. This can be implemented with relatively simple interconnections and circuits, compared that the 2-dimentional (2D) layout.

After doing a literature survey on the DFFS algorithms ([1] ~ [6]) proposed in recent years (after 2000), we select the algorithm presented in [1] to be implemented in our project. Compared with other algorithm we study in the literature survey, the selected algorithm is able to achieve highest clock frequency and spurious free dynamic range (SFDR) while requires a modest implementation complex...

We present a 6–12-GHz external modulation fiberoptic link with a spurious-free dynamic range (SFDR) of 65.5 dB MHz. This result validates an analytical model for external modulation link performance which we have updated from a previously published model to account for the use of a travelingwave external modulator. Using the revised model, we compare the expected performance of two different li...