A fundamental feature of Dynamically Recon gurable FPGAs (DRFPGAs) is that the logic and interconnect is timemultiplexed. Thus for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a di erent time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a s...

ed state machines Deterministic state machines 1. State machine extraction (e.g. stg_extract) 2. Eliminate conditions New constraints in ITL 3. Sequential circuits 5. Logic synthesis 4. Sythesizer (tableau and determinize) KISS2 interface Figure 2: Flow of Our Redesign Method 4 A Redesign Method We cannot handle very complex ITL formulas within a reasonable time, since the expansion time grows ...

In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing all flip-flops (FF’s) and clustering the combinational part of the sequential circuit. This approach breaks ...

The work presented here is set in line with fields of theoretical computer science and biology that study Boolean automata networks frequently seen as models of genetic regulation networks. In the context of biological regulation, former studies have highlighted the importance of circuits on the asymptotic dynamical behaviour of regulation networks. This is why we first chose to concentrate on ...