In this paper we shall study the multipliers on Banach algebras and We prove some results concerning Arens regularity and amenability of the Banach algebra M(A) of all multipliers on a given Banach algebra A. We also show that, under special hypotheses, each Jordan multiplier on a Banach algebra without order is a multiplier. Finally, we present some applications of m...

A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2m CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC’s) with 6-b resolution.

In this paper a new approach is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. To illustrate the proposed technique, a CMOS circuit for simultaneous realization of the logic functions NOT, OR, NAND a...

Novel low-voltage, low-power techniques in the design of portable wireless communication systems are required. Two system examples of low-power analog multipliers operating from a 1.2 V supply are presented. These proposed structures achieve the required multiplication function by using current processing. The circuits were fabricated using standard double-poly CMOS processes for a 900 MHz appl...

A method to achieve maximally fast (rate-optimal) recursive filters implemented using distributed arithmetic is presented. The filters will have the same upper bound on the sample frequency as if they were implemented using bit-serial multipliers and adders. Maximally fast implementation is important for high-speed recursive filters, but also as any excess speed can be traded for low power cons...

A study and comparison between current mode CMOS analog multiplier, CMOS current mode multiplier/divider and high frequency four quadrant current multiplier has been carried out in this paper. Current multiplier has been simulated in SPICE with 0.35μm, 0.5μm. Simulation have been done with supply voltage of 3.3V, 1.5V and 1.55V respectively. The simulated results show that characteristic of mul...

We document that government spending multipliers depend on the population age structure. Using variation in military and birth rates across US states, we show local fiscal multiplier is 1.5 increases with share of young people, implying 1.1–1.9 interquartile range. A parsimonious life cycle open economy New Keynesian model credit market imperfections age-specific differences labor supply demand...

In this paper, we present a novel high-speed lowcomplexity four data-path 128-point radix-2 FFT/IFFT processor for high-throughput MB-OFDM UWB systems. The high radix radix-2 multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. A method for compensating the truncation error of fixed-width Booth...

Digital Signal Processing (DSP) often involves multiplications with a fixed set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error of the computation, our approach scales the original coefficients to enable the partitioning of each m...