Extreme-scale parallel systems will require alternative methods for applications to maintain current levels of uninterrupted execution. Redundant computation is one approach to consider, if the benefits of increased resiliency outweigh the cost of consuming additional resources. We describe a transparent redundancy approach for MPI applications and detail two different implementations that prov...

Local feature detection and description have gained a lot of interest in recent years since photometric descriptors computed for interest regions have proven to be very successful in many applications. In this paper, we propose a novel interest region descriptor which combines the strengths of the well-known SIFT descriptor and the LBP texture operator. It is called the center-symmetric local b...

Minimizing clock skew is important in the design of high performance VLSI systems. We present a general clock routing scheme that achieves very small clock skews while still using a reasonable amount of wirelength. Our routing solution is based on the construction of a binary tree using geometric matching. For cell-based designs, the total wirelength of our clock routing tree is on average with...

In this paper, we present new results on the automated generalization of performance-related heuristics learned for knowledge-lean applications. By rst applying genetics-based learning to learn new heuristics for some small subsets of test cases in a problem space, we study methods to generalize these heuristics to unlearned subdomains of test cases. Our method uses a new statistical metric cal...

Housing mobility programs enable families living in high-poverty neighborhoods to relocate to lowerpoverty neighborhoods using tenant-based subsidies. Recent research indicates that these programs improve participant outcomes on a number of economic and social outcomes. Can such programs be run at a scale sufficient to help a large proportion of eligible families? Would doing so change the char...

Analyzing the effect of crosstalk on delay is critical for high performance circuits. The major bottleneck in performing crosstalkinduced delay analysis is the high computational cost of simulating the coupled interconnect and the nonlinear drivers. In this work, we propose an efficient iterative algorithm that avoids time-consuming nonlinear driver simulations and performs node-specific crosst...

In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise. Bounding load capacitance also improves reliability with respect to hot-carrier oxide breakdown and AC self-heating in interconnects, and guarantees boun...