We propose, simulate and experimentally demonstrate a method for realizing spatially-mapped birefringence onto integrated photonic devices and circuits. The fabrication method is based on applying a damascene-like process to dielectric film stacks to form anisotropic optical waveguides. An integrated polarizing beam-splitter (PBS) is realized with unprecedented performance: a record 0.52 octave...

We studied electromigration (EM) lifetimes and void growth at low cumulative failure probability. We carried out EM test in damascene Cu lines using sudden-death type test structures. Its cumulative failure probability ranges from 0.005 to 90%. To investigate the void growth behaviour, Cu microstructures was investigated. EM lifetime shows correlation with the void nucleation site and the void ...

Three-dimensional (3D) integration with through-die vias offer improved electrical performance compared to edgeconnected wire bonds in stacked-die assemblies. Monolithic wafer-level 3D integration offers the potential for a high density of micron-sized through-die vias necessary for highest performance of integrated systems. In addition, such wafer-level technologies offer the potential of lowe...

5 Damascene Process 5 History of Copper Interconnects 6 Damascene Process Steps 6 State of the Art in ECD 6 Electrochemical Deposition (ECD) 8 Basic ECD 11 V-I Curves 12 Uniformity 14 Boundary Layer 14 Conductivity 15 Bath Chemistry and Plating Waveforms 16 Superfilling 17 Morphology 17 A Look to the Future c o n t e n t s Interconnects in integrated circuits distribute clock and other signals ...

The constant demand to scale down transistors and improve device performance has led to material as well as process changes in the formation of IC interconnect. Traditionally, aluminum has been used to form the IC interconnects. The process involved subtractive etching of blanket aluminum as defined by the patterned photo resist. However, the scaling and performance demands have led to transiti...