Abstract Most error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of were used to improve hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control T...

Overcoming the IC power challenge requires signal energy recovery, which can be achieved utilizing adiabatic charging principles and logically reversible computing in the circuit design. This paper demonstrates the energyefficiency of a Bennett-clocked adiabatic CMOS multiplier via a simulation model. The design is analyzed on the logic gate level to determine an estimate for the number of irre...

We present a novel set of reversible modular multipliers applicable to quantum computing, derived from three classical techniques: 1) traditional integer division, 2) Montgomery residue arithmetic [1], and 3) Barrett reduction [2]. Each multiplier computes an exact result for all binary input values, while maintaining the asymptotic resource complexity of a single (non-modular) integer multipli...

Arithmetic Logic Unit (ALU) is a heart of microprocessor and microcontroller units that are playing main role in digital computers. By optimizing the ALU circuit in microprocessor and microcontroller highly power efficient digital system can be achieved. The use of low power and high performance sub-blocks like adder and multiplier can reduce the total power dissipation of ALU. So in this paper...

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design mandatory for efficient systems. In designing low-energy dissipation circuits, reversible logic more than irreversible circuits but at cost higher complexity. This paper introduces an signed/unsigned 4 × Vedic multiplier with minimum quantum cost. The considered fast a...