basis structure. The design is generic and scalable, which allows better performance when more parallel sub-units are implemented.

A three-dimensional, self-reconfigurable structure is proposed. The structure is a fully distributed system composed of many identical 3-D units. Each unit has functions of changing local connection, information processing, and communication among neighborhood units. Groups of units cooperate to change their connection so that the shape of the whole solid structure transforms into arbitrary sha...

Multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All the building blocks of the proposed reconfigurable multiplier can either work as independent smallerprecision multipliers or work in ...

A novel architecture for the testing of enhanced data rates for GSM evolution (EDGE) networks is proposed, in which a reconfigurable radio platform is used to implement up to 16 EDGE physical layers in a RF baseband module (RFBBM). When the RFBBM is used in conjunction with a line server unit (LSU), a complete mobile station emulator (MSE) is formed. In this paper, the implementation and interf...

This paper presents an efficient architecture for performing 128 points to 1M points Fast Fourier Transformation (FFT) based on mixed radix-2/4/8 butterfly unit. The proposed FFT architecture reduces the computation cost by taking the advantage of the radix-8 FFT algorithm while remaining compatible with sequences whose data length is an integral power of 2. Further optimizations for reconfigur...

Increasing complexity of system design and shorter time-to-market requirements lead research towards the investigation of hybrid systems including processors enhanced by programmable logic [1][2]. A dynamically reconfigurable processing unit tightly connected to a Flash EEPROM memory subsystem is presented. The reconfigurable processing unit targets image-voice processing and recognition applic...

Extensible processors allow customization for an application by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit. Custom instructions (CIs) usually are extracted from critical portions of applications. This paper presents approaches fo...

Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are usually extracted from critical portions of applications. It may not be possible to meet all of the RFU constraints when CIs are generated. This paper addresses the generation of mappable CIs on an ...

Reconfigurable Systems-on-a-Chip (SoC) architectures consist of microprocessors and Field Programmable Gate Arrays (FPGAs). In order to implement runtime reconfigurable systems, these SoC devices combine the ease of programmability and the flexibility that FPGAs provide. One representative of these is the new Xilinx Zynq-7000 Extensible Processing Platform (EPP), which integrates a dual-core AR...

The evolvable hardware paradigm facilitates the construction of autonomous systems that can adapt to environmental changes and degrading effects in the computational resources. Extending these scenarios, we study the capability of evolvable hardware classifiers to adapt to intentional run-time fluctuations in the available resources, i.e., chip area, in this work. To that end, we leverage the F...