This paper presents a design of low power, area efficient radix 4 booth multiplier using gated diffusion input(GDI) technique and modified gated diffusion input technique. MGDI and GDI plays an important role in design of low power and area efficient circuits. This has led many researchers to take GDI and MGDI technique very seriously in building important circuits related to advanced low power...

In this paper we designed a low hardware cost and fast DSP unit for 32-bit embedded EISC (Expanded Instruction Set Computer) microprocessor. The DSP unit operates as a functional unit of a integer core. This architecture can reduce the hardware cost and control easily the pipeline of the processor. The MAC/MAS unit was designed using hybrid radix-4/radix-8 Booth algorithm to reduce the hardware...

Two’s complement multipliers are important for a wide range of applications. Paper describes a technique to reduce by one row the maximum height of the partial product array generated by Radix-4 Booth’s multiplier, without any increase in the delay of the partial product generation stage. The design of 8 bit and 16 bit multiplication scheme using different types of multiplier like Array multipl...

In modern sciences and technologies, images have a broader scope due to growing importance of scientific visualization. Due to this image compression and manipulation is of major interest in research. In this paper, DCT architecture is proposed to deal with the truncation errors and to obtain a high throughput. Compensation architecture is done for the error due to truncation during multiplicat...

Computational demanding public key cryptographic algorithms, such as RivestShamir-Adleman (RSA) and Elliptic Curve (EC) cryptosystems, are critically dependent on modular multiplication for their performance. Modular multiplication used in cryptography may be performed in two different algebraic structures, namely GF (N) and GF (2), which normally require distinct hardware solutions for speedin...

In this paper, we present an engineering of preencoded multipliers for Digital Signal Processing applications based on disconnected encoding of coefficients. To this augment, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding method, which utilizes the digit values {-1, 0, +1, +2} or {-2,1,0,+1} is proposed prompting to a multiplier outline with less unpredictable incomplete items executio...

We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carry-based adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4...

This paper presents a high speed and low complexity modified radix-2 512-point Fast Fourier transform (FFT) architecture using an eight data-path pipelined approach for high rate wireless personal area network applications. A novel modified radix-2 FFT algorithm that reduces the hardware complexity is proposed. This method can reduce the number of complex multiplications and the size of the twi...

In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (N/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (r≥3) multiplication. Based on a mathematical proof t...

Although division is less frequent than addition and multiplication, because of its longer latency it dissipates a substantial part of the energy in floating-point units. In this paper we explore the relation between the radix and the energy dissipated. Previous work has been done on radix-4 and radix-8 division. Here we extend this study to a radix16 scheme with two overlapped radix-4 stages a...