The Micronet-based Asynchronous Processor (MAP) is a family of processor architectures based on the micronet model of asynchronous control. Micronets distribute the control amongst the functional units which enables the exploitation of ne-grained concurrency, both between and within program instructions. This paper introduces the mi-cronet model and evaluates the performance of micronet-based d...

A distributed program is presented that ensures delivery of a message to the functioning processors in a computer network, despite the fact that processors may fail at any time. All processor failures are assumed to be detected and to result in halting the offending processor. A reliable communications network is assumed.

Finding the root cause of power-based side-channel leakage becomes harder when multiple layers design abstraction are involved. While originates in processor hardware, dangerous consequences may only become apparent cryptographic software that runs on processor. This contribution presents RootCanal, a methodology to explain origin program terms underlying micro-architecture and system architect...

In this paper we introduce a framework for computing upper bounds yet accurate WCET for hardware platforms with caches and pipelines. The methodology we propose consists of 3 steps: 1) given a program to analyse, compute an equivalent (WCET-wise) abstract program; 2) build a timed game by composing this abstract program with a network of timed automata modeling the architecture; and 3) compute ...

If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The basic idea is that the tester loads a program along with compressed test data into the processor’s on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the o...

Providing untrusted applications with shared and dependable access to modern display hardware is of increasing importance. Our new display system, called Blink, safely multiplexes complex graphical content from multiple untrusted virtual machines onto a single Graphics Processing Unit (GPU). Blink does not allow clients to program the GPU directly, but instead provides a virtual processor abstr...

The variety of parallel architectures nowadays available implies that models for parallel software development should deliver acceptable performance on a range of architectures with minimal development effort. One approach is to use languages with very high level, and substantially architecture-independent, specification of parallel coordination. This paper presents a novel profiling-based meth...

This paper evaluates an automatic power reduction scheme of OSCAR automatic parallelizing compiler having power reduction control capability when multiple media applications parallelized by the OSCAR compiler are executed simultaneously on RP2, a 8-core multicore processor developed by Renesas Electronics, Hitachi, and Waseda University. OSCAR compiler enables the hierarchical multigrain parall...

The design and implementation of a real-time super-resolution imaging processor was conducted as a benchmark for the Rapid Prototyping of Application Specific Signal Processors (RASSP) program. RASSP is a DARPA/Tri-services sponsored program aimed at accelerating the design process for digital electronic systems. The super-resolution subsystem is part of a Semi-Automated Image-intelligence Proc...