Abstract: Power consumption is considered as one of the important challenge in modern VLSI design along with area and speed consideration. Flip flop plays very important role in digital systems. In this paper comparative study of four different flip flops which includes pulse triggered as well as conditional technique flip flop such as IP-DCO, MHLFF, CPSFF, and CPFF topologies in sub threshold ...

Application of Generalized Power Delay Metrics to Supply and Threshold Selection in Deep Submicron CMOS by Dipanjan Sengupta Power consumption has become as important as performance in todays deep submicron designs. As a result, high-level techniques and models must be developed to evaluate design changes in terms of power (energy) and performance tradeoff early in the design process. Recently,...

abstract: this paper is the first study on the impact of ambient temperature on the electrical characteristics and high frequency performances of double gate armchair graphene nanoribbon field effect transistor (gnrfet). the results illustrate that the gnrfet under high temperature (ht-gnrfet) has the highest cut-off frequency, lowest sub-threshold swing, lowest intrinsic delay and power delay ...

The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissible interconnect widths and spaces to very few discrete values with some interdependencies, making traditional interconnect sizing by continuous-variable optimization techniques impossible. Single-net bottom-up power-delay optimization for discrete wire widths has been solved and got a lot of atten...

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set , , . In this manuscript we h...

Parallel prefix addition is a technique for speeding up binary addition. Classical parallel prefix adder structures developed so far are optimized for logic depth, area, fan-out and interconnect count of logic circuits. Due to continuing integrating intensity and growing needs of portable devices, low-power and high-performance designs are of prime importance. A new technique, proposed for perf...

The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissible interconnect widths and spaces to very few discrete values with some interdependencies, making traditional interconnect sizing by continuous-variable optimization techniques impossible. Single-net bottom-up power-delay optimization for discrete wire widths has been solved and got a lot of atten...

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circu...