Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that during logic synthesis power tracks well with area. This means that a larger design will generally consume more power. The multiplier is an important kernel of ...

With the appearance of high performance mobile devices, low cost and low power consumption have become important issues in high performance processors. To meet the needs, low cost and low power floating-point fused multiply-add unit is proposed in this paper. According to the area and power consumption analysis, the multiplication part in fused multiplyadd operation accounted for most power con...

Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...

For large high-speed globally synchronous ASICs, designing the clock distribution net becomes a troublesome task. Besides problems caused by clock skew, the clock net also is a major source of power consumption. Partitioning the design into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces power consumption. However, to achieve these positive effects, t...

Applications of wearable and implanted wireless sensor devices are hot research area. A specialized field called the body area networks (BAN) has emerged to support this area. Managing and controlling such a network is a challenging task. An efficient media access control (MAC) protocol to handle proper management of media access can considerably improve the performance of such a network. Power...

Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. To reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the high-level synthesis stage. However, previous work may suffer from a large circuit area overhead on the clock control logic. In this paper, we present an I...

Due to the high density and the low consumption power in the digital integrated circuits, mostly technology of CMOS is used. During the past times, the Metal oxide silicon field effect transistors (MOSFET) had been used for the design and implementation of the digital integrated circuits because they are compact and also they have the less consumption power and delay to the other transistors. B...