We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suit...

In this paper we develop a set of interconnect delay estimation models with consideration of various layout optimizations, including optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous bu er insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90% accuracy on average compared with those ...

As a traditional model in the operations research and management science domain, deterministic lot-sizing problem is embedded in many application problems such as production and inventory planning and has been consistently drawing attentions from researchers. In this paper we consider basic versions of lot-sizing models in which problem parameters are stochastic and develop corresponding scenar...

In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-optimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of “globally” optimal wire widths for a range of interconn...

Optimal placement and sizing of DG in distribution network is an optimization problem with continuous and discrete variables. Many researchers have used evolutionary methods for finding the optimal DG placement. This paper proposes a shuffled frog leaping algorithm (SFLA) for optimal placement and sizing of distributed generation (DG) in radial distribution system to minimize the total real pow...