In this study, a improved software architecture named M_AUTOSAR based on the standard AUTOSAR is introduced which can upgrade the software system performance in multi-core microprocessors system for automotive system design. At the beginning of this paper, based on the analysis of the existing development trend of embedded multi-core microprocessors, we refined and improved infrastructure based...

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dualand quad-core) vs_ single core processor systems. Analysis of processor design, application source code, and...

This paper explores the problem of energy optimization in embedded platforms. Specifically, it studies resource allocation strategies for meeting performance constraints with minimal energy consumption. We present a comparison of solutions for both homogeneous and single-ISA heterogeneous multi-core embedded systems. We demonstrate that different hardware platforms have fundamentally different ...

Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memor...

We present the effects of L1 and L2 cache sharing on cache miss rates, cache line invalidations, and constuctive and destructive interference. The most important finding of this paper is that a system configuration that shares L2 caches, does not share L1 caches, and does not enforce inclusion between the L1 and L2 caches will produce the highest performance cache and communication hierarchy fo...

Designing embedded systems has become a complex and expensive task, and simulation and other analysis tools are taking on a bigger role in the overall design process. In an effort to speed up the design process, we present an algorithm for reducing the simulation time of large, complex models by creating a parallel schedule from a flattened set of equations that collectively capture the system ...

Article history: Available online 4 September 2013

A number of important system services, particularly network system services, need strong scaling on multi-core systems, where a fixed workload is executed more quickly with increased core counts. Unfortunately, modern multiple-instruction/multipledata (MIMD) approaches to multi-core OS design cannot exploit the fine-grained parallelism needed to provide such scaling. In this paper, we propose a...

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