A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits to a range of logical values, thus forming a special class of analog circuits. The idea of this work is to exploit this relationship for testing. For fault modeling the behavior of faulty fuzzy gates is investigated th...

This paper presents novel techniques for timing yield optimization and for yield estimation in the presence of large statistical process variations in integrated circuits. The techniques are based on our generalization of the logical effort delay model to circuits with stochastic parameter variations. In the spirit of the standard logical effort formalism, the stochastic gate delay model we pro...

With the anticipated end of Moore’s law for integrated circuits [3, 4] fast approaching and continued advances in low-power electronics, interest in quantum computing has increased. This shifts the focus from deterministic logical circuits to potentially more powerful circuits based on controllable quantum systems. In this column, we present a mathematical tour of the quantum circuit model, beg...

The logical test of integrated VLSI circuits is one of the main phases of their design and fabrication. The pseudo-exhaustive approach for the logical test of integrated circuits consists in partitioning the original circuit to be tested into non-overlapping subcircuits with a small, bounded number of subcircuits, which are then exhaustively tested in parallel. In this work we present an approx...

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands...

The verification of timed digital circuits is an important issue. These circuits are composed by logical gates, each of them being associated with propagation delays. The analysis of such circuits is necessary to identify critical path and adjust the clock period of the circuit or to determine the stability period of input/ouput signals. These circuits are represented by a functional model desc...

In this paper we consider the problem of routing the lightpaths of a logical topology of a WDM network on an arbitrary physical topology, such that the logical topology remains connected even after the failure of a physical link. We focus our attention on the ring interconnection as the logical topology because it is widely used in many protection schemes. We first establish the necessary and s...

Collaborative indicators derived from quantitative statistical indicators of students’ interactions in forums can be used by e-learning systems in order to support the collaborative behaviour and motivation of students. The main objective of this research is to achieve a transferable and domain-independent reputation indicator, considering the information extracted from social network analysis,...

This paper presents a new framework for formal logic veri cation. What is depicted here is fundamentally di erent from previous approaches. In earlier appraoches, the circuit is either not changed during the veri cation process, as in OBDD or implicationbased methods, or the circuit is progressively reduced during veri cation. Whereas in our approach, we actually enlarge the circuits by adding ...

Field-Programmable Gate Arrays (FPGAs) are integrated circuits that implement reconfigurable hardware. They are used in modern systems, creating specialized, highly-optimized integrated circuits without the need to design and manufacture dedicated chips. As the capacity of FPGAs grows, it is increasingly common for designers to incorporate implementations of algorithms and protocols from a rang...