This paper describes the circuit design of a programmable logic array chip using four-phase dynamic circuits, operating at a nominal cycle time of 230 nanoseconds. Bootstrap circuit techniques are used to obtain high function and performance by satisfying some special requirements of PLA designs. These include a simple means for two-bit partitioning of the data inputs, a noninverting buffer cir...

The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. After recent improvement techniques on PLA, PLA becomes more attractive for designers especially in GHz technology with deep sub-micron sizing. In this paper we will try to introduce the cross-talk problem solution in DSM, in PLA Network and also try to give the usage of PLA in GHz technology and the ad...

A cellular logic image processor employing 192 cells in a 16 by 12 hexagonal array is described . The processor has been constructed and its performance assessed . The various classes of functions which can be implemented in the cellular array are discussed and sample programs explained in detail . Cellular array Pattern recognition Image processing Parallel processing Binary images

In this paper, for the first time to our knowledge, we investigate the optical bi-stability in a compact parallel array of micro- ring resonators with 5μm radius, induced by optical nonlinearity. Due to the nature of perfect light confinement, resonance and accumulation process in a ring resonator, optical nonlinear effects, even at small optical power of a few milliwatts in this structure are ...

In this paper, we have design of ternary 2x2 Sram memory Array using carbon Nano-tube field-effect transistors (CNTFETs).the CNTFET technology has new parameters and characteristics which determine the performances such as current driving capability, speed, power consumption and area of circuits have been proposed for ternary 2x2 Sram memory array is needed to optimize performance using CNTFET ...

Control Loop Feedback Mechanism for Generic Array Logic Chip Multiprocessor is presented. The approach is based on control-loop feedback mechanism to maximize the efficiency on exploiting available resources such as CPU time, operating frequency, etc. Each Processing Element (PE) in the architecture is equipped with a frequency scaling module responsible for tuning the frequency of processors a...

Abstract According to tradition, logic is normative for reasoning. many contemporary philosophers of logic, there more than one correct logic. What the relationship between these two strands thought? This paper makes claims. First, doubly reasoning because, in addition constraining combinations beliefs that we may have, also constrains methods by which form them. Second, given reasoning, a wide...