Multifunction Vehicle Bus controllers (MVBC) are safetycritical sub-systems in the industrial train communication network. As an interrupt-driven system, MVBC is practically hard to verify. The reasons are twofold. First, MVBC introduces the concurrency semantics of deferred interrupt handlers and communication via hardware registers, making existing formalism infeasible. Second, verifying MVBC...

The hardware cost of taking an interrupt is increasing as processors become more superscalar. Using FLIP, an aggressively superscalar processor which we have designed and tested in Verilog, we demonstrate that interrupts can be fast and inexpensive. We trace individual signals through FLIP’s pipeline stages to show that fast interrupts require negligible new hardware. Except for linkage informa...

Most of the research effort towards verification of concurrent software has focused on multithreaded code. On the other hand, concurrency in low-end embedded systems is predominantly based on interrupts. Low-end embedded systems are ubiquitous in safety-critical applications such as those supporting transportation and medical automation; their verification is important. Although interrupts are ...

INTERRUPT RESPONSE TIME The Am29000 processor is free of microcode which can greatly influence a systems interrupt architecture. Typically, when an interrupt occurs on a CISC type processor, a context frame is saved on a memory stack. A 29K Family user is not constrained by built-in microcode and is free to construct a scheme which reduces overheads and better suits real-time system requirements.

Interrupts are a key design primitive for embedded software that interacts closely with hardware. The interrupt mechanism enables timely response to outside stimuli in a power-efficient way. Interrupts are common in all styles of computing platforms, including safety-critical embedded software, low-power mobile platforms, and high-end information systems. But interrupt-driven code is difficult ...