Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Sev...

A methodology is proposed and demonstrated for the direct passive synthesis of SPICE-compatible models of multi-conductor interconnect structures. The algorithm is based on a PadéChebyshev approximation of the frequency-dependent input impedance matrix of the passive interconnect system. Given the bandwidth of simulation, the length of the interconnect system, and its per-unit-length, frequency...

Recent studies showed that conventional approaches being used to solve problems imposed by hard-wired metal interconnects will eventually encounter fundamental limits and may impede the advance of future ultralarge-scale integrated circuits (ULSIs). To surpass these fundamental limits, we introduce a novel RF/wireless interconnect concept for future interand intra-ULSI communications. Unlike th...